Down to the Last Meter

In 1988, a consortium led by AT&T switched on TAT-8, the first transatlantic fiber optic cable. It carried roughly ten times the traffic of TAT-7, the last analog coaxial cable laid across the Atlantic. At that distance the comparison was not close, and copper never competed again.

The distance at which light beats copper has been shrinking ever since. Fiber took the routes between cities, then the links between buildings, then the connections between rows in a data center, then the hops between racks in the same room. At the data rates now entering AI clusters, a copper cable carries a clean signal for about a meter. The current frontier is the switch package itself, where optical engines are mounted on the same substrate as the switch silicon rather than in a module at the front panel.

The energy cost of moving data

The usual mental model of a computer puts the processor at the center. It does the work; the wires carry results around. Sixty years of process improvements went into the processor, and the wiring was assumed to follow along.

The energy accounting no longer supports that picture. Mark Horowitz's widely cited 2014 figures for a 45nm process put a 32-bit floating point add at under a picojoule and a 32-bit DRAM read at several hundred picojoules, a ratio of a few hundred to one. Both numbers have moved since, but not together. Arithmetic energy has fallen sharply with each process node, while memory access energy has improved far more slowly because it's governed by wire capacitance and interface physics rather than transistor scaling, and the gap has widened.

How much of a system's energy this accounts for depends heavily on the workload. The most-cited measurement comes from a 2018 study of Google's consumer mobile workloads, which attributed 62.7% of total system energy to data movement, a figure cited in Mutlu et al.'s survey on processing in memory. That is a different machine from a training cluster, and the figure should not be transplanted directly. But the direction holds across the processing-in-memory literature: on data-intensive workloads, moving operands costs more than operating on them, and every joule spent moving a bit ends up as heat in a rack.

Copper at 224 gigabits

Once movement dominates, performance becomes partly a question of geometry: how far apart the parts are, and what connects them.

This matters now because frontier training runs stopped fitting on single chips years ago. Tens of thousands of accelerators have to behave as one machine, which makes the network between them a component of the processor rather than infrastructure around it.

Electrical signaling degrades with both distance and data rate. Synopsys puts the reach of a copper backplane channel at roughly 2.5 meters at 112 Gbps per lane, falling to about one meter at 224 Gbps. Those are channel-class figures rather than hard physical limits: Marvell has demonstrated a 224G long-reach SerDes driving 2.5 meters of copper at low bit error rate, and Nvidia's Rubin generation doubles per-lane bandwidth using bidirectional SerDes over the same physical wires. Copper is being pushed hard, and it's not finished. But the trend line is clear enough that crossing a server cabinet electrically is now a design constraint rather than an assumption.

The industry's answer for the past decade has been to convert to light at the switch faceplate. A pluggable transceiver takes an electrical signal, converts it to laser light, and sends it down a fiber. Inside sits a digital signal processor that retimes and reconditions the signal after its 15 to 30 centimeter journey from the ASIC, and that also handles PAM4 modulation. SemiAnalysis puts the DSP at close to half the power of an 800G SR8 module. The approach works, and it built the modern data center, but the conversion is expensive at scale. At GTC 2025, Jensen Huang laid out the arithmetic: six transceivers per GPU, roughly 30 watts each, which comes to about 180 megawatts of transceiver power for a million-GPU cluster.

Co-packaged optics moves the optical engine onto the switch package, millimeters to tens of millimeters from the switch silicon rather than tens of centimeters. The long electrical run disappears, and with it the DSP and much of the amplification and retiming. Nvidia's Quantum-X photonic switch shipped in the second half of 2025, with the Ethernet Spectrum-X version following in 2026. Nvidia claims a 3.5x reduction in interconnect power and four times fewer lasers. TSMC has built a dedicated integration platform, COUPE, for stacking photonic and electronic dies.

What the first generation changes

Less than the power figures suggest. SemiAnalysis models networking at around 9% of total cluster power for a three-layer GB300 NVL72 cluster. A 23% reduction in networking power therefore yields about 2% at the cluster level. Flattening to a two-layer network does better, roughly 4%, but neither is transformative. Cost savings are similarly diluted once switch vendor margin on the optical engines is accounted for.

Volumes reflect this. SemiAnalysis expects total shipments of 10 to 15 thousand CPO scale-out switches in 2026. The first generation is largely a supply chain exercise: getting fiber attach, laser reliability, and field servicing understood at production scale before the technology is needed somewhere it can't be avoided.

That place is the scale-up fabric, the links that let a rack of GPUs act as one large accelerator. Fifth-generation NVLink moves 7.2 Tbit/s per GPU, roughly nine times what the same GPU sends across the scale-out network, and copper's two-meter reach at those speeds caps how many GPUs can share a scale-up domain. Nvidia's response so far has been to build denser racks: the Kyber architecture packs four times the density of GB200/GB300 NVL72, which is why power delivery and liquid cooling have become the binding constraints they are. Optics would remove the reach limit and let scale-up domains span racks.

It's not the only candidate. Co-packaged copper, which brings twinax cabling directly off the package substrate and bypasses lossy PCB traces, is simpler to manufacture and is being seriously evaluated as the path to 448G signaling. The likely outcome is hybrid: copper where it still reaches, optics where it doesn't, with the boundary continuing to move inward.

Why it took so long

The physics was never the obstacle: the problems were manufacturing ones. First, attaching hair-thin fibers to silicon at yield, with fiber pitches around 127 microns and a largely manual alignment step. Second, keeping lasers alive next to hot silicon, which is why most designs now use external laser sources in pluggable modules. And third, servicing a switch whose optics cannot be unplugged when something fails: a single optical engine failure can take out 64 ports. Meta's ECOC 2025 reliability study with Broadcom is encouraging on this last point, showing better mean time between failures for CPO than for equivalent pluggables, but it covers fifteen switches in a lab over about eleven months. That's not yet a production data set.

Co-packaged optics shipped when the packaging matured, years after the concept was understood. The companies that solved fiber attach and laser reliability are the reason the roadmap works.

The broader point is that the constraint on large-scale compute has been drifting away from arithmetic for some time: first toward memory, now toward the interconnect. Capability roadmaps that are denominated only in FLOPS miss where the engineering effort and the capital are going. Packaging, photonics, and thermal design are doing as much of the work as process nodes, and each further crossover from copper to light will look, from the outside, like the machines simply got faster.